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1-/2-channel 15 v digital potentiometer ad5260/ad5262 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2010 analog devices, inc. all rights reserved. features 256 positions ad5260: 1 channel ad5262: 2 channels (independently programmable) potentiometer replacement 20 k, 50 k, 200 k low temperature coefficient: 35 ppm/c 4-wire, spi-compatible serial data input 5 v to 15 v single-supply; 5.5 v dual-supply operation power on midscale preset applications mechanical potentiometer replacement instrumentation: gain, offset adjustment stereo channel audio level control programmable voltage-to-current conversion programmable filters, delays, time constants line impedance matching low resolution dac replacement general description the ad5260/ad5262 provide a single- or dual-channel, 256- position, digitally controlled variable resistor (vr) device. 1 these devices perform the same electronic adjustment function as a potentiometer or variable resistor. each channel of the ad5260/ad5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the spi-compatible serial-input register. the resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the vr latch. the variable resistor offers a completely programmable value of resistance, between the a terminal and the wiper or the b terminal and the wiper. the fixed a-to-b terminal resistance of 20 , 50 , or 200 has a nominal temperature coefficient of 35 ppm/c. unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 v or 5 v provided proper supply voltages are furnished. each vr has its own vr latch that holds its programmed resistance value. these vr latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. the ad5260 contains an 8-bit serial register whereas the ad5262 contains a 9-bit serial register. each bit is clocked into the register on the positive functional block diagrams rdac register logic 8 power-on reset serial input register ad5260 s hdn v dd v ss v l cs clk sdi gnd a wb sdo pr 02695-001 figure 1. ad5260 rdac1 register rdac2 register logic 8 power-on reset serial input register ad5262 shdn v dd v ss v l cs clk sdi gnd a 1w1b1 a2w2b2 sdo pr 02695-002 figure 2. ad5262 edge of the clk pin. the ad5262 address bit determines the corresponding vr latch to be loaded with the last eight bits of the data word during the positive edging of cs strobe. a serial data output pin at the opposite end of the serial register enables simple daisy-chaining in multiple vr applications without additional external decoding logic. an optional reset pin ( pr ) forces the wiper to the midscale position by loading 0x80 into the vr latch. the ad5260/ad5262 are available in thin surface-mount 14-lead tssop and 16-lead tssop packages. all parts are guaranteed to operate over the extended industrial temperature range of ?40c to +85c. 1 the terms digital potentiometers, vr, and rdac are used interchangeably.
ad5260/ad5262 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristics20 k, 50 k, 200 k versions .. 3 ? timing diagrams.......................................................................... 5 ? absolute maximum ratings............................................................ 6 ? esd caution.................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 9 ? test circuits..................................................................................... 14 ? theory of operation ...................................................................... 15 ? digital interfacing ...................................................................... 15 ? daisy-chain operation ............................................................. 16 ? rdac structure.......................................................................... 16 ? programming the variable resistor......................................... 16 ? programming the potentiometer divider ............................... 17 ? layout and power supply bypassing ....................................... 18 ? terminal voltage operating range ......................................... 18 ? power-up sequence ................................................................... 18 ? rdac circuit simulation model............................................. 18 ? macro model net list for rdac ............................................. 18 ? applications information .............................................................. 19 ? bipolar dc or ac operation from dual supplies................. 19 ? gain control compensation .................................................... 19 ? programmable voltage reference ............................................ 19 ? 8-bit bipolar dac ...................................................................... 19 ? bipolar programmable gain amplifier................................... 20 ? programmable voltage source with boosted output ........... 20 ? programmable 4 ma-to-20 ma current source ................... 20 ? programmable bidirectional current source......................... 21 ? programmable low-pass filter ................................................ 21 ? programmable oscillator .......................................................... 21 ? resistance scaling ...................................................................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 24 ? revision history 8/10rev. 0 to rev. a updated format..................................................................universal deleted figure 1; renumbered sequentially................................. 1 changes to general description section ...................................... 1 changes to conditions of channel resistance matching (ad5262 only) parameter, voltage divider temperature coefficient parameter, full-scale error parameter, and zero- scale error parameter, table 1 ........................................................ 3 changes to table 2 and table 3....................................................... 5 changes to table 4............................................................................ 6 changes to table 5............................................................................ 7 changes to table 6............................................................................ 8 changes to figure 11 caption and figure 12 ................................9 changes to figure 31...................................................................... 12 changes to figure 35 caption ...................................................... 13 changes to figure 43 and figure 46............................................. 14 deleted potentiometer family selection guide ......................... 18 change to programmable voltage source with boosted output section.............................................................................................. 20 changes to figure 64...................................................................... 21 updated outline dimensions....................................................... 23 changes to ordering guide .......................................................... 24 3/02revision 0: initial version
ad5260/ad5262 rev. a | page 3 of 24 specifications electrical characteristics20 k, 50 k, 200 k versions v dd = +15 v, v ss = 0 v, or v dd = +5 v, v ss = C5 v; v l = +5 v; v a = +5 v, v b = 0 v, ?40c < t a < +85c, unless otherwise noted. the ad5260/ad5262 contain 1968 transistors. die size: 89 mil 105 mil (9345 sq mil). table 1. parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode sp ecifications apply to all vrs resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1 ? +1 lsb resistor nonlinearity 2 r-inl r wb , v a = no connect ?1 ? +1 lsb nominal resistor tolerance 3 r ab t a = 25c ?30 30 % resistance temperature coefficient r ab /t wiper = no connect 35 ppm/c wiper resistance r w i w = 1 v/r ab 60 150 channel resistance matching (ad5262 only) r wb /r wb channel 1 and channel 2 r wb , d x = 0x80 0.1 % resistance drift r ab 0.05 % dc characteristics potentiometer divider mode specifications apply to all vrs resolution n 8 bits differential nonlinearity 4 dnl ?1 1/4 +1 lsb integral nonlinearity 4 inl ?1 1/2 +1 lsb voltage divider temperature coefficient v w /t code = half scale 5 ppm/c full-scale error w fse code = full scale ?2 ?1 +0 lsb zero-scale error v wzse code = zero scale 0 1 2 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v ax and bx capacitance 6 c a,b f = 5 mhz, measured to gnd, code = half scale 25 pf wx capacitance 6 c w f = 1 mhz, measured to gnd, code = half scale 55 pf common-mode leakage current i cm v a = v b = v dd /2 1 na shutdown current 7 i shdn 5 a digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v l = 3 v, v ss = 0 v 2.1 v input logic low v il v l = 3 v, v ss = 0 v 0.6 v output logic high (sdo) v oh r pull-up = 2 k to 5 v 4.9 v output logic low (sdo) v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current 8 i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies logic supply v l 2.7 5.5 v power single-supply range v dd range v ss = 0 v 4.5 16.5 v power dual-supply range v dd/ss range 4.5 5.5 v logic supply current i l v l = 5 v 60 a positive supply current i dd v ih = 5 v or v il = 0 v 1 a negative supply current i ss v ss = ?5 v 1 a power dissipation 9 p diss v ih = 5 v or v il = 0 v, v dd = +5 v, v ss = C5 v 0.3 mw power supply sensitivity pss v dd = +5 v, 10% 0.003 0.01 %/%
ad5260/ad5262 rev. a | page 4 of 24 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 10 bandwidth C3 db bw r ab = 20 k/50 k/200 k 310/130/30 khz total harmonic distortion thd w v a = 1 v rms , v b = 0 v, f = 1 khz, r ab = 20 k 0.014 % v w settling time t s v a = +5 v, v b = ?5 v, 1 lsb error band, r ab = 20 k 5 s crosstalk 11 c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full-scale code change (ad5262 only) 1 nv-sec analog crosstalk c ta v a1 = v dd , v b1 = 0 v, measure v w1 with v w2 = 5 v p-p at f = 10 khz, r ab = 20 k/200 k (ad5262 only) C64 db resistor noise voltage e n_wb r wb = 20 k, f = 1 khz 13 nv/hz interface timing characteristics 6 , 12 specifications apply to all parts clock frequency f clk 25 mhz input clock pulse width t ch , t cl clock level high or low 20 ns data setup time t ds 10 ns data hold time t dh 10 ns clk to sdo propagation delay 13 t pd r l = 1 k, c l < 20 pf 1 160 ns cs setup time t css 5 ns cs high pulse width t csw 20 ns reset pulse width t rs 50 ns clk fall to cs rise hold time t csh 0 ns cs rise to clock rise setup t cs1 10 ns 1 typical values represent av erage readings at 25c and v dd = +5 v, v ss = ? 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +5 v and v ss = ?5v. 3 v ab = v dd , wiper = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider simil ar to a voltage output digital-to-analog converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminal a, ter minal b, and terminal w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the ax terminals. all ax terminals are open-circuit in shutdown mode. 8 worst-case supply current consumed when all logic-input levels set at 2.4 v, which is the standard characteristic of cmos logi c. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = +5 v, v ss = ?5 v, v l = +5 v. 11 measured at v w where an adjacent v w is making a full-scale voltage change. 12 see figure 5 for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using v l = 5 v. 13 propagation delay depends on value of v dd , r l , and c l .
ad5260/ad5262 rev. a | page 5 of 24 timing diagrams table 2. ad5260 8-bit serial data word format data b7 (msb) b6 b5 b4 b3 b2 b1 b0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 table 3. ad5262 9-bit serial data word format addr data b8 b7 (msb) b6 b5 b4 b3 b2 b1 b0 (lsb) a0 d7 d6 d5 d4 d3 d2 d1 d0 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 rdac register load cs d7 d6 d5 d4 d3 d2 d1 d0 sdi 1 0 clk 1 0 1 0 v out 1 0 0 2695-004 figure 3. ad5260 timing diagram rdac register load cs d7a0 d6 d5 d4 d3 d2 d1 d0 sdi 1 0 clk 1 0 1 0 v out 1 0 02695-005 figure 4. ad5262 timing diagram 1 0 1 0 1 0 1 0 v dd v out 0v 1 lsb 1 lsb error brand ax or dx a'x or d'x dx d'x t ds t ch t s t cl t css t pd t dh t csh t cs1 t csw cs sdo (data out) sdi (data in) clk 02695-006 figure 5. detailed timing diagram pr 1 0 v dd 0v 1 lsb error band 1 lsbd t rs t s 02695-007 figure 6. preset timing diagram
ad5260/ad5262 rev. a | page 6 of 24 absolute maximum ratings t a =25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +17 v v ss to gnd 0 v to ?7 v v dd to v ss 17 v v l to gnd 0 v to +7 v v a , v b , v w to gnd v ss , v dd a x to b x , a x to w x , b x to w x intermittent 1 20 ma continuous 5 ma digital inputs and output voltage to gnd ?0.3 v to v l + 0.3 v, or +7 v (whichever is less) operating temperature range ?40c to +85c maximum junction temperature (t j max ) 150c storage temperature range ?65c to +150c lead temperature (soldering,10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c thermal resistance 2 ja 14-lead tssop 206c/w 16-lead tssop 150c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance setting. 2 package power dissipation = (t j max ? t a )/ ja .
ad5260/ad5262 rev. a | page 7 of 24 pin configurations and function descriptions ad5260 nc = no connect 1 2 3 4 5 6 7 w b v dd sdi clk s hdn a 14 13 12 11 10 9 8 nc v l v ss cs pr gnd sdo top view (not to scale) 0 2695-008 figure 7. ad5260 pin configuration table 5. ad5260 pin function descriptions pin o. nemonic description 1 a a terminal. 2 w wiper terminal. 3 b b terminal. 4 v dd positive power supply. specified for operation at both 5 v or 15 v (sum of |v dd | + |v ss | 15 v). 5 shdn active low input. terminal a, open-circuit. shutdown controls variable resistor. 6 clk serial clock input, positive edge triggered. 7 sdi serial data input. 8 cs chip select input, active low. when cs returns high, data is loaded into the rdac register. 9 pr active low preset to midscale. sets rdac registers to 0x80. 10 gnd ground. 11 v ss negative power supply. specified for operation from 0 v to ?5 v. 12 v l logic supply voltage. needs to be the same volt age as the digital logic controlling the ad5260. 13 nc no connect. users should not connect anything other than a dummy pad on this pin. 14 sdo serial data output. open-drain transistor requires a pull-up resistor.
ad5260/ad5262 rev. a | page 8 of 24 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad5262 top view (not to scale) w1 b1 v dd sdi clk shdn a1 w2 b2 a2 sdo v l v ss cs pr gnd 02695-009 figure 8. ad5262 pin configuration table 6. ad5262 pin function descriptions pin o. nemonic description 1 sdo serial data output. open-drain transistor requires a pull-up resistor. 2 a1 a terminal rdac 1. 3 w1 wiper rdac 1, address a0 = 0. 4 b1 b terminal rdac 1. 5 v dd positive power supply. specified for operation at both 5 v or 15 v. (sum of |v dd | + |v ss | 15 v) 6 shdn active low input. terminal a, open-circuit. shutdown controls variable resistor 1 through resistor r2. 7 clk serial clock input, positive edge triggered. 8 sdi serial data input. 9 cs chip select input, active low. when cs returns high, data in the serial input register is decoded, based on the address bit a0, and loaded into the target rdac register. 10 pr active low preset to midscale. sets rdac registers to 0x80. 11 gnd ground. 12 v ss negative power supply. specified for operati on at either 0 v or ?5 v (sum of |v dd | + |v ss | < 15 v). 13 v l logic supply voltage. needs to be same voltag e as the digital logic controlling the ad5262. 14 b2 b terminal rdac 2. 15 w2 wiper rdac 2, address a0 = 1. 16 a2 a terminal rdac 2.
ad5260/ad5262 rev. a | page 9 of 24 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) t a = ?40c t a = +25c t a = +85c t a = +125c code (decimal) 0 32 64 96 128 160 192 224 256 02695-013 v dd = +5v v ss = ?5v r ab = 20k ? code (decimal) rheostat mode inl (lsb) ?0.2 ?0.1 0.1 0 0 32 64 96 128 160 192 224 256 0.2 0.3 0.4 0.5 0.6 0.7 0.8 +15v +5v 5v +12v 02695-010 figure 12. dnl vs. code figure 9. r-inl vs. code vs. supply voltages ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer mode inl (lsb) +15v +5v 5v 02695-014 code (decimal) rheostat mode dnl (lsb) ?0.25 0 32 64 96 128 160 192 224 256 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 +15v +12v +5v 5v 02695-011 figure 13. inl vs. code vs. supply voltages figure 10. r-dnl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 0 32 64 96 128 160 192 224 256 code (decimal) +15v +5v 5v 02695-015 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer mode inl (lsb) v dd = +5v t a = +125c t a = +85c t a = ?40c t a = +25c v ss = ?5v r ab = 20k ? 02695-012 figure 14. dnl vs. code vs. supply voltages figure 11. inl vs. code
ad5260/ad5262 rev. a | page 10 of 24 ?1.0 ?0.5 0 0.5 1.0 0 5 10 15 20 |v dd ? v ss | (v) potentiometer mode inl (lsb) avg ? 3 avg avg + 3 02695-016 figure 15. inl vs. supply voltages ?2.0 ?1.0 ?1.5 ?0.5 0 0.5 2.0 1.0 1.5 05 10 15 20 |v dd ? v ss | (v) rheost a t mode inl (lsb) avg ? 3 avg avg + 3 02695-017 figure 16. r-inl vs. supply voltages 4 24 44 64 84 104 124 ?5 ?1 3 7 11 15 v dd (v) wiper resistance ( ? ) r on @ v dd /v ss = +5v/0v r on @ v dd /v ss = +5v/?5v r on @ v dd /v ss = +15v/0v 02695-018 figure 17. wiper on resistance vs. bias voltage 0 0.5 1.0 1.5 2.0 2.5 ?40 ?20 0 20 40 60 80 100 temperature (c) fse (lsb) v dd /v ss =+5v/0v v dd /v ss =+15/0v v dd /v ss =5v 02695-019 figure 18. full-scale error vs. temperature 0 0.5 1.0 1.5 2.0 2.5 ?40 ?20 0 20 40 60 80 100 temperature (c) zse (lsb) v dd /v ss =+15/0v v dd /v ss =5v v dd /v ss =+5v/0v 02695-020 figure 19. zero-scale error vs. temperature 0.001 0.01 0.1 1 ?40?726599212 temperature (c) i dd /i ss supply current (a) 5 v logic = 5v v ih = 5v v il = 0v v dd /v ss = 5v v dd /v ss = +15/0v 02695-021 figure 20. supply current vs. temperature
ad5260/ad5262 rev. a | page 11 of 24 24.5 25.0 25.5 26.0 26.5 27.0 27.5 28.0 ?40?7 26599212 temperature (c) i logic (a) 5 v dd /v ss = 5v v dd /v ss = +15/0v 0 2695-022 figure 21. i logic vs. temperature 10 100 1000 0 1.0 2.0 3.0 4.0 0.5 1.5 2.5 3.5 4.5 5.0 v ih (v) i logic (a) 02695-023 v dd /v ss = 5v/0v v logic = 5v v dd /v ss = 5v/0v v logic = 3v figure 22. i logic vs. digital input voltage ?20 ?10 0 10 20 30 40 50 60 70 80 0 32 64 96 128 160 192 224 256 code (decimal) rheost a t mode tempco (ppm/c) 50k ? 20k ? 200k ? 02695-024 figure 23. rheostat mode tempco r wb /t vs. code ?60 ?40 ?20 0 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 code (decimal) potentiometer mode tempco (ppm/c) 50k ? 20k ? 200k ? 02695-025 figure 24. potentiometer mode tempco v wb /t vs. code frequency (hz) gain (db) 1k 1m 6 ?48 ?54 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k code = 0xff 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 t a = 25c 02695-026 figure 25. gain vs. frequency vs. code, r ab = 20 k frequency (hz) gain (db) 1k 1m 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k code = 0xff 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 t a = 25c 02695-027 ?54 figure 26. gain vs. frequency vs. code, r ab = 50 k
ad5260/ad5262 rev. a | page 12 of 24 frequency (hz) gain (db) 1k 1m ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k t a = 25c code = 0xff 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 02695-028 figure 27. gain vs. frequency vs. code, r ab = 200 k frequency (hz) 1k 1m 10k 100k ?3db bandwidths v in = 50mv rms v dd /v ss = 5v f ?3db = 30khz, r = 200k ? f ?3db = 131khz, r = 50k ? f ?3db = 310khz, r = 20k ? gain (db) ?54 6 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 02695-029 figure 28. ?3 db bandwidth frequency (hz) normalized gain flatness (db) 100 100k 1k 0 0.1 0.2 0.3 ?0.4 ?0.3 ?0.2 ?0.7 ?0.6 ?0.5 ?0.1 10k code = 0x80 v dd /v ss = 5v t a = 25c r = 200k ? r = 50k ? r = 20k ? 02695-030 figure 29. normalized ga in flatness vs. frequency frequency (hz) i logic (a) 10k 10m 100k 600 300 400 500 0 100 200 1m code 0xff code 0x55 v dd /v ss = 5v v dd /v ss = +5v/0v 02695-031 figure 30. i logic vs. frequency frequency (hz) psrr (db) 100 1m 0 60 10k 10 1k 20 30 40 50 100k ?psrr @ v dd = 5v dc 10% p-p ac +psrr @ v dd = 5v dc 10% p-p ac code = 0x80, v a = v dd , v b = 0v 02695-032 figure 31. psrr vs. frequency 20mv/div 1s/div 5v/div 02695-033 figure 32. midscale glitch energy, code 0x80 to 0x7f
ad5260/ad5262 rev. a | page 13 of 24 hours of operation at 150c change in terminal resi s tance (%) 05 ?0.20 0.10 ?0.10 0 0.05 0 0 100 200 250 300 350 400 450 avg ? 3 50 150 ?0.05 ?0.15 avg + 3 avg 0 2695-037 code = 0x80 v dd /v ss = 5v sample size = 135 units 5v/div 20s/div 5v/div 02695-034 figure 36. long-term resistance drift figure 33. large signal settling time channel-to-channel r ab match (%) frequency ?0.50 0 40 30 code set to midscale t a = 150c 3 lots sample size = 135 units 20 10 ?0.40 ?0.30 ?0.20 ?0.10 0 0.10 0.20 02695-038 10mv/div 40ns/div 02695-035 figure 34. digital feedthrough vs. time figure 37. channel-to-channel resistance matching (ad5262) code (decimal) theoretic a l i wb_max (ma) 02 0.01 100 0.1 1 10 5 6 32 64 96 128 160 192 224 v a = v b = open t a = 25c r ab = 20k ? r ab = 50k ? r ab = 200k ? 02695-036 figure 35. theoretical maximum current vs. code
ad5260/ad5262 rev. a | page 14 of 24 test circuits figure 38 to figure 46 define the test conditions used in table 1 . v ms a w b dut v + = v dd 1lsb = v+/2 n v+ 02695-039 figure 38. potentiometer divider nonlinearity error (inl, dnl) nc i w v ms a w b dut nc = no connect 02695-040 figure 39. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) i w = v dd /r nominal v ms2 v w v ms1 r w = (v ms1 ? v ms2 )/i w a w b dut 02695-041 figure 40. wiper resistance pss (%/%) = v+ = v dd 10% psrr (db) = 20 log ? v ms ? v dd ? v ms % ? v dd % () v dd v a v ms a w b v+ 02695-042 figure 41. power supply sensitivity (pss, pssr) +13v ?13v w a b v out offset gnd dut ad8610 v in 0 2695-043 figure 42. gain vs. frequency w b v ss to v dd dut code = 0x00 r w = 0.1v i w i w 0.1v a = nc 02695-044 figure 43. incremental on resistance w b i cm a nc gnd nc v ss v cm v dd dut 02695-045 figure 44. common-mode leakage current sdi clk cs v logic i logic digital input voltage 02695-046 figure 45. v logic current vs. digital input voltage a1 rdac1 rdac2 w1 nc b1 a2 w2 b2 c ta = 20 log (v out /v in ) nc = no connect v in v out v ss v dd 02695-047 figure 46. analog crosstalk
ad5260/ad5262 rev. a | page 15 of 24 theory of operation the ad5260/ad5262 provide a single- or dual-channel, 256- position, digitally controlled variable resistor (vr) device and operate up to 15 v maximum voltage. changing the programmed vr settings is accomplished by clocking an 8-/9-bit serial data word into the sdi (serial data input) pin. for the ad5262, the format of this data word is one address bit. a0 represents the first bit, b8, followed by eight data bits, b7 to b0, with msb first. table 2 and table 3 provide the serial register data word format. see table 7 for the ad5262 address assignment to decode the location of the vr latch receiving the serial register data in bit b7 through bit b0. vr outputs can be changed one at a time in random sequence. the ad5260/ad5262 preset to a midscale, simplifying fault condition recovery at power-up. midscale can also be achieved at any time by asserting the pr pin. both parts have an internal power-on preset that places the wiper in a midscale preset condition at power-on. operation of the power- on preset function depends only on the state of the v l pin. the ad5260/ad5262 contain a power shutdown shdn pin that places the rdac in an almost zero power consumption state where terminals ax are open circuited and the wiper w is connected to b, resulting in only leakage currents being con- sumed in the vr structure. in the shutdown mode, the vr latch settings are maintained so that, when returning to operational mode from power shutdown, the vr settings return to their previous resistance values. table 7. ad5262 address decode table a0 latch loaded 0 rdac1 1 rdac2 digital interfacing the ad5260/ad5262 contain a 4-wire spi-compatible digital interface (sdi, sdo, cs , and clk). for the ad5260, the 8-bit serial word must be loaded with the msb first. the format of the word is shown in . for the ad5262, the 9-bit serial word must be loaded with address bit a0 first, then the msb of the data. the format of the word is shown in . table 2 table 3 a0 ser reg d7 d6 d5 d4 d3 d2 d1 d0 a1 w1 b1 v dd cs clk sdo a2 w2 b2 gnd rdac latch 2 pr rdac latch 1 pr pr sdi v l v ss shdn power- on preset en addr dec 02695-048 figure 47. ad5262 block diagram the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. stand- ard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. figure 47 shows more detail of the inter- nal digital circuitry. when cs is low, the clock loads data into the serial input register on each positive clock edge (see ). table 8 table 8. truth table 1 clk cs pr shdn register activity low low high high no sr effect, enables sdo pin. low high high shift one bit in from the sdi pin. the eighth previously entered bit is shifted out of the sdo pin. x high high load sr data into rdac latch. x high high high no operation. x x low high sets all rdac latches to half scale, wiper centered, and sdo latch cleared. x high high latches all rdac latches to 0x80. x high high low open circuits all resistor a terminals, connects w to b, and turns off sdo output transistor. 1 = positive edge, x = dont care, sr = shift register. the data setup and data hold times in table 1 determine the data valid time requirements. the ad5260 uses an 8-bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic high. for the ad5262, the last nine bits of the data word entered into the serial register are held when cs returns high. any extra bits are ignored. at the same time cs goes high, it gates the address decoder, enabling one of two positive edge-triggered ad5262 rdac latches (see ). figure 48
ad5260/ad5262 rev. a | page 16 of 24 rdac1 rdac2 ad5260/ad5262 sdi clk cs addr decode serial register 02695-049 figure 48. equivalent input control logic the target rdac latch is loaded with the last eight bits of the serial data word completing one rdac update. for the ad5262, two separate 9-bit data words must be clocked in to change both vr settings. during shutdown ( shdn ), the sdo output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. see for the equivalent sdo output circuit schematic. figure 49 sdi clk cs shdn pr serial register dq ck rs sdo 02695-050 figure 49. detail sdo output schematic of the ad5260 all digital inputs are protected with a series input resistor and parallel zener esd structure as shown in figure 50 . this applies to the cs , sdi, sdo, pr , shdn , and clk digital input pins. 340 ? logic 02695-051 figure 50. esd protection of digital pins a, b, w v ss 02695-052 figure 51. esd protection of resistor terminals daisy-chain operation the serial data output (sdo) pin contains an open-drain n- channel fet. this output requires a pull-up resistor to transfer data to the sdi pin of the next package. this allows for daisy- chaining several rdacs from a single processor serial data line. the pull-up resistor termination voltage can be larger than the v dd supply voltage. it is recommended to increase the clock period when using a pull-up resistor to the sdi pin of the following device in series because capacitive loading at the daisy-chain node connecting sdo and sdi between devices may induce time delay to subsequent devices. users should be aware of this potential problem to achieve data transfer successfully (see figure 52 ). if two ad5260s are daisy-chained, this requires a total of 16 bits of data. the first eight bits, complying with the format shown in table 2 , go to u2, and the second eight bits with the same format go to u1. the cs pin should be kept low until all 16 bits are clocked into their respective serial registers, and the cs pin is then pulled high to complete the operation. v dd cs clk sdo sdi mosi micro- controller sclk ss r p 2.2k ? ad5260 ad5260 u1 u2 02695-055 cs clk sdo sdi figure 52. daisy-chain configuration rdac structure the rdac contains a string of equal resistor segments with an array of analog switches that act as the wiper connection. the number of positions is the resolution of the device. the ad5260/ ad5262 have 256 connection points, allowing it to provide better than 0.4% settability resolution. figure 53 shows an equivalent structure of the connections between the three terminals that make up one channel of the rdac. sw a and sw b are always on, while one of the switches sw(0) to sw(2 n C 1) is on one at a time, depending on the resistance position decoded from the data bits. because the switch is not ideal, there is a 60 wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage is, the higher the wiper resistance becomes. similarly, the higher the temperature is, the higher the wiper resistance becomes. users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed. d7 d6 d5 d4 d3 d2 d1 d0 rdac latch and decode ax wx bx r s = r ab /2 n r s r s r s r s s hdn digital circuitry omitted for clarity 02695-056 figure 53. simplified rdac architecture programming the variable resistor rheostat operation the nominal resistances of the rdac between terminal a and terminal b are available with values of 20 k, 50 k, and 200 k. the final three digits of the part number determine the nominal resistance value, for example, 20 k = 20, 50 k = 50, 200 k = 200. the nominal resistance (r ab ) of the vr has 256 contact points
ad5260/ad5262 rev. a | page 17 of 24 accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assuming a 20 k part is used, the wipers first connection starts at the b terminal for data 0x00. because there is a 60 wiper contact resistance, such a connection yields a minimum of 60 resistance between terminal w and terminal b. the second connection is the first tap point corresponding to 138 (r wb = r ab /256 r w = 78 + 60 ) for data 0x01. the third connection is the next tap point representing 216 (78 2 + 60) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19,982 (r ab ? 1 lsb + r w ). the wiper does not directly connect to the b terminal. see figure 53 for a simplified diagram of the equivalent rdac circuit. the general equation determining the digitally programmed output resistance between w and b is w ab wb rr d dr += 256 )( (1) where d is the decimal equivalent of the binary code that is loaded in the 8-bit rdac register and r ab is the nominal end- to-end resistance. for example, when r ab = 20 k, v b = 0 v, and the a terminal is open circuit, the following output resistance values of r wb are set for the rdac latch codes shown in tabl e 9 . the result is the same if terminal a is tied to w. table 9. r wb vs. code rdac (dec) r wb () output state 256 19,982 full scale (r ab C 1 lsb + r w ) 128 10,060 midscale 1 138 1 lsb 0 60 zero-scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 60 is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. like the mechanical potentiometer the rdac replaces, the ad5260/ad5262 are completely symmetrical. the resistance between wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . figure 54 shows the symmetrical programmability of the various terminal connec- tions. when r wa is used, the b terminal can be left floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general equation for this operation is w ab wa rr d dr + ? = 256 256 )( (2) for example, when r ab = 20 k, v a = 0 v, and the b terminal is open circuit, the following output resistance values of r wa are set for the rdac latch codes shown in tabl e 10 . the result is the same if terminal b is tied to terminal w. table 10. r wa vs. code rdac (dec) r wa () output state 256 60 full scale 128 10,060 half scale 1 19,982 1 lsb 0 20,060 zero scale r wa r wb r ab = 20k ? code (decimal) 20 0 64 128 192 256 r wa (d), r wb (d) ? k ? 16 12 8 4 0 02695-057 figure 54. ad5260/ad5262 equivalent rdac circuit the typical distribution of the nominal resistance r ab from channel to channel matches within 1%. device-to-device matching is process lot-dependent with the worst case of 30% variation. however, because the resistance element is processed in thin film technology, the change in r ab with temperature has a low 35 ppm/c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper-to-b and wiper-to-a to be proportional to the input voltage at a-to-b. ignore the effect of the wiper resistance. for example, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at w-to-b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 256 positions of the potentiometer divider. because the ad5260/ad5262 operate from dual supplies, the general equation defining the output voltage at v w with respect to ground for any given input voltage applied to terminal a and terminal b is b ab w vv d dv += 256 )( (3) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors, r wa and r wb , and not the absolute values; therefore, the drift reduces to 5 ppm/c.
ad5260/ad5262 rev. a | page 18 of 24 layout and power supply bypassing it is good practice to employ a compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (see figure 55 ). note that the digital ground should also be joined remotely to the analog ground to minimize the ground bounce. v ss v dd v ss v dd c3 c4 c1 c2 10f 10f gnd 0.1f 0.1f + + 02695-053 figure 55. power supply bypassing terminal voltage operating range the ad5260/ad5262 positive v dd and negative v ss power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on the a, b, and w terminals that exceed v dd or v ss are clamped by the internal forward-biased diodes (see figure 56 ). v dd v ss a w b 02695-054 figure 56. maximum terminal voltages set by v dd and v ss the ground pin of the ad5260/ad5262 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the pcb. the digital input control signals to the ad5260/ad5262 must be referenced to the device ground pin (gnd), and must satisfy the logic level defined in table 1 . an internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from v ss to v dd regardless of the digital input level. power-up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w (see figure 56 ), it is important to power v dd /v ss first before applying any voltage to the a, b, and w terminals. otherwise, the diode becomes forward biased such that v dd /v ss are powered unintentionally and may affect the rest of the users circuit. the ideal power-up sequence is in the following order: gnd, v dd , v ss , v l , the digital inputs, and v a /v b /v w . the order of powering v a /v b /v w and the digital inputs is not important as long as they are powered after v dd /v ss . rdac circuit simulation model the internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the rdacs. configured as a potentiometer divider, the ?3 db bandwidth of the ad5260 (20 k resistor) measures 310 khz at half scale. figure 28 provides the large signal bode plot characteristics of the three available resistor versions 20 k, 50 k, and 200 k. a parasitic simula- tion model is shown in figure 57 . the following section provides a macro model net list for the 20 k rdac. ab 55pf c b 25pf c a 25pf c w rdac 20k ? w 02695-071 figure 57. rdac circuit simulation model for rdac 20 k macro model net list for rdac param d=256, rdac=20e3 * subckt dpot (a,w,b) * ca a 0 25e-12 rwa a w {(1-d/256)*rdac+60} cw w 0 55e-12 rwb w b {d/256*rdac+60} cb b 0 25e-12 * .ends dpot
ad5260/ad5262 rev. a | page 19 of 24 applications information bipolar dc or ac operation from dual supplies the ad5260/ad5262 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. the ac signal, as high as v dd /v ss , can be applied directly across terminal a and terminal b with output taken from terminal w. see figure 58 for a typical circuit connection. +5.0v clk cs gnd v dd sdi gnd v dd v ss ?5.0v sclk mosi microcontroller ss 5v p-p 2.5v p-p d = 0x80 02695-058 figure 58. bipolar operat ion from dual supplies gain control compensation digital potentiometers are commonly used in gain control as in the noninverting gain amplifier shown in figure 59 . u1 v o w b a r2 200k ? c2 4.7pf v i r1 47k ? c1 25pf 02695-059 figure 59. typical noninvertng gain amplifier note that when the rdac b terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/ o term with +20 db/dec, whereas a typical op amp gain bandwidth product (gbp) has ?20 db/dec characteristics. a large r2 and finite c1 can cause this zeros frequency to fall well below the crossover frequency. therefore, the rate of closure becomes 40 db/dec and the system has 0 phase margin at the crossover frequency. the output may ring or oscillate if the input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. depending on the op amp gbp, reducing the feedback resistor may extend the zeros frequency far enough to overcome the problem. a better approach, however, is to include a compensa- tion capacitor, c2, to cancel the effect caused by c1. optimum compensation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, the r1 c1 = r2 c2 relationship can be used, and scale c2 as if r2 is at its maximum value. doing so may overcompensate and compromise the performance slightly when r2 is set at low values. however, it avoids the ringing or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of a few picofarads (pf) to no more than a few tenths of pf is usually adequate for the compensation. similarly, there are w and a terminal capacitances connected to the output (not shown). fortunately, their effect at this node is less significant, and the compensation can be avoided in most cases. programmable voltage reference for voltage divider mode operation, shown in figure 60 , it is common to buffer the output of the digital potentiometer unless the load is much larger than r wb . not only does the buffer serve the purpose of impedance conversion, but it also allows a heavier load to be driven. a1 v o 5v v in gnd v out 5v ad1582 u1 ad8601 1 2 3 a w b ad5260 02695-060 figure 60. programmable voltage reference 8-bit bipolar dac figure 61 shows a low cost 8-bit bipolar dac. it offers the same number of adjustable steps but not the precision of conventional dacs. the linearity and temperature coefficients, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. the output of this circuit is ref o v d v 1 256 2 (4) a2 ?5v op2177 ba w w1 a1 v o +5 v ?5v +5v u2 +5v ref ?5v ref v in v out gnd trim ad5260 v i adr425 r r u1 op2177 02695-061 figure 61. 8-bit bipolar dac
ad5260/ad5262 rev. a | page 20 of 24 bipolar programmable gain amplifier for applications that require bipolar gain, figure 62 shows one implementation. digital potentiometer u1 sets the adjustment range. the wiper voltage at w2 can therefore be programmed between v i and ?kv i at a given u2 setting. configuring a2 in the noninverting mode allows linear gain and attenuation. the transfer function is () ? ? ? ? ? ? ?+ ? ? ? ? ? ? += kk d r1 r2 v v i o 1 256 2 1 (5) where k is the ratio of r wb1 /r wa 1 set by u1. ?kv i a1 b1 a2 r1 r2 v dd v ss v ss v dd op2177 op2177 a2 b2 w2 u2 ad5262 u1 ad5262 w1 a1 v o c1 v i 02695-062 figure 62. bipolar programmable gain amplifier similar to the previous example, in the simpler and more common case, where k = 1, with a single digital potentiometer, ad5260, u1 is replaced by a matched pair of resistors to apply v i and ?v i at the ends of the digital potentiometer. the relation- ship becomes i o v d r1 r2 v ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 256 22 1 (6) if r2 is large, a few picofarad compensation capacitors may be needed to avoid any gain peaking. table 11 shows the result of adjusting d, with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 256-step resolution. table 11. result of bipolar gain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 ?1 ?2 ?10 64 ?0.5 ?1 ?5 128 0 0 0 192 +0.5 +1 +5 255 +0.968 +1.937 +9.680 programmable voltage source with boosted output for applications that require high current adjustment such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 63 ). v i a1 v o w u1 a b c c i l 5 v signal lo n1 r1 10k ? p1 r bias u1 = ad5260 a1 = ad8601, ad8605, ad8541 p1 = fdp360p, nds9430 n1 = fdv301n, 2n7002 02695-063 figure 63. programmable boosted voltage source in this circuit, the inverting input of the op amp forces v o to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the p-channel fet, p1. the n-channel fet, n 1 , simplifies the op amp driving requirement. a1 must be the rail-to-rail input type. resistor r1 is needed to prevent p1 from turning off once it is on. the choice of r1 is a balance between the power loss of this resistor and the output turn-off time. n1 can be any general-purpose signal fet. however, p1 is driven in the saturation state, and there- fore, its power handling must be adequate to dissipate (v i ? v o ) i l power. this circuit can source a maximum of 100 ma at 5 v supply. higher current can be achieved with p1 in a larger pack- age. note that a single n-channel fet can replace p1, n1, and r1 altogether. however, the output swing is limited unless sepa- rate power supplies are used. for a precision application, a voltage reference such as the adr423 , adr292 , or ad1584 can be applied at the input of the digital potentiometer. programmable 4 ma-to-20 ma current source a programmable 4 ma-to-20 ma current source can be implemented with the circuit shown in figure 64 . ref191 is a unique low supply headroom and high current handling precision reference that can deliver 20 ma at 2.048 v. the load current is simply the voltage across terminal b to terminal w of the digital potentiometer, divided by r s . s ref l r dv i = (7)
ad5260/ad5262 rev. a | page 21 of 24 ?5v op1177 + ? u2 +5v r s 102 ? r l 100 ? v l i l a b w ad5260 c1 1f gnd ref191 sleep v s output +5v u1 2 3 4 6 0v to (2.048v + v l ) ?2.048 to v l 02695-064 figure 64. programmable 4-to-20 ma current source the circuit is simple, but be aware that dual-supply op amps are ideal because the ground potential of ref191 can swing from ?2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the programmable resolution of the system is reduced. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution (see figure 65 ). if the resistors are matched, the load current is w l v br r1brar i 2 22 (8) ad8016 +15v ?15v +5v ?5v op2177 ad5260 a1 w a b c2 10pf r1' 150k ? r1 150k ? r2' 15k ? a2 c1 10pf r2a 14.95k ? r l 500 ? r l 50 ? +15v ?15v v l i l 02695-065 figure 65. programmable bidirectional current source programmable low-pass filter digital potentiometer ad5262 can be used to construct a second-order, sallen-key low-pass filter (see figure 66 ). the design equations are 2 2 2 o o o i o s q s v v (9) r1r2c1c2 o 1 z (10) r2c2 r1c1 q 11 (11) users can first select any convenient value for the capacitors. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2. as a result, users can adjust r1 and r2 to the same settings to achieve the desirable bandwidth. a b v i ad8601 +2.5v v o ?2.5v w r r2 r1 a b w r c1 c2 adjusted to same settings 02695-066 figure 66. sallen key low-pass filter programmable oscillator in a classic wien-bridge oscillator (see figure 67 ), the wien network (r, r, c, c) provides positive feedback, whereas r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. with r = r, c = c, and r2 = r2a//(r2b + r diode ), the oscillation frequency is r c o 1 z or r c f o s 2 1 (12) where r is equal to r wa such that ab r d r 256 256 (13) at resonance, setting 2 r1 r2 (14) balances the bridge. in practice, r2/r1 should be set slightly larger than 2 to ensure the oscillation can start. however, the alternate turn-on of the diodes, d1 and d2, ensures r2/r1 to be smaller than 2 momentarily and therefore stabilizes the oscillation. when the frequency is set, the oscillation amplitude can be tuned by r2b because d d o vbriv 2 3 2 (15) v o , i d , and v d are interdependent variables. with proper selection of r2b, an equilibrium is reached such that v o converges. r2b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output. in both circuits in figure 66 and figure 67 , the frequency tuning requires that both rdacs be adjusted to the same settings. because the two channels are adjusted one at a time, an intermedi-
ad5260/ad5262 rev. a | page 22 of 24 d ts can be programmed to the same setting simultaneously. ate state occurs that may not be acceptable for certain applications. as a result, different devices can also be used in daisy-chaine mode so that par in voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in figure 69 . the equivalent resistance becomes w eqwb rr2r1 d r + = )//( 256 _ (16) +5v op1177 v o ?5v r2a 2.1k ? d1 d2 r2b 10k ? vn r1 1k? ab w r1 = r1' = r2b = ad5262 d1 = d2 = 1n4148 ad5262 c' 2.2nf r' 10k ? ab w vp c 2.2nf frequenc y adjustment r 10k ? a b w u1 amplitude w eqwa rr2r1 d r + ? ? ? ? ? ? ?= )//( 256 1 _ (17) w a b r2 r1 r2 << r1 02695-069 figure 69. lowering the nominal resistance adjustment 02695- 067 cillator with amplitude control le o program both channels coherently with the same settings. figure 68 and figure 69 show that the digital potentiometers change steps linearly. however, log taper adjustment is usually preferred in applications like audio control. figure 70 shows another method of resistance scalin g. in this circuit, the smaller r2 is with respect to r ab , the more the pseudo-log taper characteristic behaves. figure 67. programmable os resistance scaling the ad5260/ad5262 offer 20 k, 50 k, and 200 k nominal resistance. for users who need lower resistance and still main- tain the numbers of step adjustment, they can place multip devices in parallel. for example, figure 68 shows a simple scheme of paralleling both channels of the ad5262. to adjust half of the resistance linearly per step, users need t v o a b r1 r2 v i w 02695-070 w1 a1 b1 w2 a2 b2 v ld dd 02695- figure 70. resistor scaling with log adjustment characteristics 068 68. reduce resistance by half wi th linear adjustment characteristics figure
ad5260/ad5262 rev. a | page 23 of 24 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 71. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 72. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters
ad5260/ad5262 rev. a | page 24 of 24 ordering guide model 1 rab (k) temperature package description package option no. of parts per container ad5260bruz20 20 ?40c to +85c 14-lead tssop ru-14 96 ad5260bruz20-rl7 20 ?40c to +85c 14-lead tssop ru-14 1000 ad5260bruz50 50 ?40c to +85c 14-lead tssop ru-14 96 ad5260bruz50-reel7 50 ?40c to +85c 14-lead tssop ru-14 1000 ad5260bruz200 200 ?40c to +85c 14-lead tssop ru-14 96 ad5260bruz200-rl7 200 ?40c to +85c 14-lead tssop ru-14 1000 ad5262bru20 20 ?40c to +85c 16-lead tssop ru-16 96 ad5262bru20-reel7 20 ?40c to +85c 16-lead tssop ru-16 1000 ad5262bru50 50 ?40c to +85c 16-lead tssop ru-16 96 ad5262bru50-reel7 50 ?40c to +85c 16-lead tssop ru-16 1000 ad5262bru200 200 ?40c to +85c 16-lead tssop ru-16 96 ad5262bru200-reel7 200 ?40c to +85c 16-lead tssop ru-16 1000 AD5262BRUZ20 20 ?40c to +85c 16-lead tssop ru-16 96 AD5262BRUZ20-rl7 20 ?40c to +85c 16-lead tssop ru-16 1000 ad5262bruz50 50 ?40c to +85c 16-lead tssop ru-16 96 ad5262bruz50-rl7 50 ?40c to +85c 16-lead tssop ru-16 1000 AD5262BRUZ200 200 ?40c to +85c 16-lead tssop ru-16 96 AD5262BRUZ200-rl7 200 ?40c to +85c 16-lead tssop ru-16 1000 eval-ad5262ebz evaluation board 1 z = rohs compliant part. ?2002C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02695-0-8/10(a)

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